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UInt32 | DeAd |
| | Device address.
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UInt32 | ClAd |
| | Clock address.
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UInt32 | ClVa |
| | Clock value (defaults to 2 = enabled, set to 0 = disabled).
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UInt32 | REVISION |
| | Register at offset 00h (see ARM Reference Guide, chapter 25.4.1.1 ).
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UInt32 | SYSCONFIG |
| | Register at offset 10h (see ARM Reference Guide, chapter 25.4.1.2 ).
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UInt32 | EOI |
| | Register at offset 20h (see ARM Reference Guide, chapter 25.4.1.3 ).
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UInt32 | IRQSTATUS_RAW_0 |
| | Register at offset 24h (see ARM Reference Guide, chapter 25.4.1.4 ).
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UInt32 | IRQSTATUS_RAW_1 |
| | Register at offset 28h (see ARM Reference Guide, chapter 25.4.1.5 ).
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UInt32 | IRQSTATUS_0 |
| | Register at offset 2Ch (see ARM Reference Guide, chapter 25.4.1.6 ).
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UInt32 | IRQSTATUS_1 |
| | Register at offset 30h (see ARM Reference Guide, chapter 25.4.1.7 ).
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UInt32 | IRQSTATUS_SET_0 |
| | Register at offset 34h (see ARM Reference Guide, chapter 25.4.1.8 ).
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UInt32 | IRQSTATUS_SET_1 |
| | Register at offset 38h (see ARM Reference Guide, chapter 25.4.1.9 ).
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UInt32 | IRQSTATUS_CLR_0 |
| | Register at offset 3Ch (see ARM Reference Guide, chapter 25.4.1.10 ).
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UInt32 | IRQSTATUS_CLR_1 |
| | Register at offset 40h (see ARM Reference Guide, chapter 25.4.1.11 ).
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UInt32 | IRQWAKEN_0 |
| | Register at offset 44h (see ARM Reference Guide, chapter 25.4.1.12 ).
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UInt32 | IRQWAKEN_1 |
| | Register at offset 48h (see ARM Reference Guide, chapter 25.4.1.13 ).
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UInt32 | SYSSTATUS |
| | Register at offset 114h (see ARM Reference Guide, chapter 25.4.1.14 ).
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UInt32 | CTRL |
| | Register at offset 130h (see ARM Reference Guide, chapter 25.4.1.15 ).
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UInt32 | OE |
| | Register at offset 134h (see ARM Reference Guide, chapter 25.4.1.16 ).
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UInt32 | DATAIN |
| | Register at offset 138h (see ARM Reference Guide, chapter 25.4.1.17 ).
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UInt32 | DATAOUT |
| | Register at offset 13Ch (see ARM Reference Guide, chapter 25.4.1.18 ).
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UInt32 | LEVELDETECT0 |
| | Register at offset 140h (see ARM Reference Guide, chapter 25.4.1.19 ).
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UInt32 | LEVELDETECT1 |
| | Register at offset 144h (see ARM Reference Guide, chapter 25.4.1.20 ).
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UInt32 | RISINGDETECT |
| | Register at offset 148h (see ARM Reference Guide, chapter 25.4.1.21 ).
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UInt32 | FALLINGDETECT |
| | Register at offset 14Ch (see ARM Reference Guide, chapter 25.4.1.22 ).
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UInt32 | DEBOUNCENABLE |
| | Register at offset 150h (see ARM Reference Guide, chapter 25.4.1.23 ).
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UInt32 | DEBOUNCINGTIME |
| | Register at offset 154h (see ARM Reference Guide, chapter 25.4.1.24 ).
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UInt32 | CLEARDATAOUT |
| | Register at offset 190h (see ARM Reference Guide, chapter 25.4.1.25 ).
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UInt32 | SETDATAOUT |
| | Register at offset 194h (see ARM Reference Guide, chapter 25.4.1.26 ).
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Structure for GPIO subsystem registers.
This UDT contains a set of all GPIO subsystem registers. It's used to store the initial configuration of the four subsystems in the TI AM335x CPU , and to hold their current configurations for the next call to function PruIo::config().
- Since
- 0.2
Definition at line 20 of file pruio_gpio.bi.
1.9.1