libpruio  0.6.8
Fast and easy Digital/Analog Input/Output for Beaglebones
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TimerSet Class Reference

Structure for TIMER subsystem registers. More...

Public Attributes

UInt32 DeAd
 Device address.
 
UInt32 ClAd
 Clock address.
 
UInt32 ClVa
 Clock value (defaults to 2 = enabled, set to 0 = disabled).
 
UInt32 TIDR
 Register at offset 00h (see ARM Reference Guide, chapter 20.1.5.1 ).
 
UInt32 TIOCP_CFG
 Timer OCP Configuration Register (offset 10h, see ARM Reference Guide, chapter 20.1.5.2 ).
 
UInt32 IRQ_EOI
 Timer IRQ End-of-Interrupt Register (offset 20h, see ARM Reference Guide, chapter 20.1.5.3 ).
 
UInt32 IRQSTATUS_RAW
 Timer Status Raw Register (offset 24h, see ARM Reference Guide, chapter 20.1.5.4 ).
 
UInt32 IRQSTATUS
 Timer Status Register (offset 28h, see ARM Reference Guide, chapter 20.1.5.5 ).
 
UInt32 IRQENABLE_SET
 Timer Interrupt Enable Set Register (offset 2Ch, see ARM Reference Guide, chapter 20.1.5.6 ).
 
UInt32 IRQENABLE_CLR
 Timer Interrupt Enable Clear Register (offset 30h, see ARM Reference Guide, chapter 20.1.5.7 ).
 
UInt32 IRQWAKEEN
 Timer IRQ Wakeup Enable Register (offset 34h, see ARM Reference Guide, chapter 20.1.5.8 ).
 
UInt32 TCLR
 Timer Control Register (offset 38h, see ARM Reference Guide, chapter 20.1.5.9 ).
 
UInt32 TCRR
 Timer Counter Register (offset 3Ch, see ARM Reference Guide, chapter 20.1.5.10 ).
 
UInt32 TLDR
 Timer Load Register (offset 40h, see ARM Reference Guide, chapter 20.1.5.11 ).
 
UInt32 TTGR
 Timer Trigger Register (offset 44h, see ARM Reference Guide, chapter 20.1.5.12 ).
 
UInt32 TWPS
 Timer Write Posting Bits Register (offset 48h, see ARM Reference Guide, chapter 20.1.5.13 ).
 
UInt32 TMAR
 Timer Match Register (offset 4Ch, see ARM Reference Guide, chapter 20.1.5.14 ).
 
UInt32 TCAR1
 Timer Capture Register (offset 50h, see ARM Reference Guide, chapter 20.1.5.15 ).
 
UInt32 TSICR
 Timer Synchronous Interface Control Register (offset 54h, see ARM Reference Guide, chapter 20.1.5.16 ).
 
UInt32 TCAR2
 Timer Capture Register (offset 58h, see ARM Reference Guide, chapter 20.1.5.17 ).
 

Detailed Description

Structure for TIMER subsystem registers.

This UDT contains a set of all TIMER subsystem registers. It's used to store the initial configuration of the four subsystems in the TI AM335x CPU , and to hold their current configurations for the next call to function PruIo::config().

Since
0.4

Definition at line 20 of file pruio_timer.bi.

The documentation for this class was generated from the following file: