33 #define PRUIO_VERSION "0.6.6"
49 #define PRUIO_DEF_AVRAGE 4
51 #define PRUIO_DEF_ODELAY 183
53 #define PRUIO_DEF_SDELAY 0
55 #define PRUIO_DEF_SAMPLS 1
57 #define PRUIO_DEF_STPMSK 510
59 #define PRUIO_DEF_TIMERV 0
61 #define PRUIO_DEF_LSLMOD 4
63 #define PRUIO_DEF_CLKDIV 0
495 PRUIO_PIN_RESET = 0xFF
UDT for PWM modules, containing the functions to drive the hardware.
struct pwmssArr pwmssArr
Wrapper structure for PwmssArr.
unsigned short uint16
16 bit unsigned integer data type.
BBTypes
Wrapper enumerators for board types.
@ BB_Blue
Beaglebone Blue with connectors, SD.
@ PBB2x36
PocketBeagle board with 2x36 headers, SD.
@ BBB2x46
Classic Beaglebone board with 2x46 headers, JT, SD.
struct pwmssSet pwmssSet
Wrapper structure for PwmssSet.
struct timerSet timerSet
Wrapper structure for TimerSet.
unsigned int uint32
32 bit unsigned integer data type.
signed char int8
8 bit signed integer data type.
struct gpioUdt gpioUdt
Wrapper structure for GpioUdt.
char * pruio_config(pruIo *Io, uint32 Samp, uint32 Mask, uint32 Tmr, uint16 Mds)
Wrapper function for PruIo::config().
char * pruio_mm_start(pruIo *Io, uint32 Trg1, uint32 Trg2, uint32 Trg3, uint32 Trg4)
Wrapper function for PruIo::mm_start().
uint32 pruio_adc_mm_trg_pre(pruIo *Io, uint8 Stp, int32 AdcV, uint16 Samp, uint8 Rela)
Wrapper function for AdcUdt::mm_trg_pre().
char * pruio_gpio_flush(pruIo *Io, uint8 Indx)
Wrapper function for GpioUdt::flush().
char * pruio_cap_Value(pruIo *Io, uint8 Ball, float_t *Hz, float_t *Du)
Wrapper function for CapMod::Value().
float float_t
float data type.
uint32 pruio_adc_mm_trg_ain(pruIo *Io, uint8 Stp, int32 AdcV, uint8 Rela, uint16 Skip)
Wrapper function for AdcUdt::mm_trg_ain().
short int16
16 bit signed integer data type.
char * pruio_tim_Value(pruIo *Io, uint8 Ball, float_t *Dur1, float_t *Dur2)
Wrapper function for TimerUdt::Value().
struct adcUdt adcUdt
Wrapper structure for AdcUdt.
struct capMod capMod
Wrapper structure for CapMod.
int int32
32 bit signed integer data type.
struct ballSet ballSet
Wrapper structure for BallSet.
char * pruio_pwm_setValue(pruIo *Io, uint8 Ball, float_t Hz, float_t Du)
Wrapper function for PwmMod::setValue().
struct gpioSet gpioSet
Wrapper structure for GpioSet.
char * pruio_Pin(pruIo *Io, uint8 Ball)
Wrapper function for PruIo::Pin().
struct pwmssUdt pwmssUdt
Wrapper structure for PwmssUdt.
uint32 pruio_gpio_Value(pruIo *Io, uint8 Ball)
Wrapper function for GpioUdt::Value().
pruIo * pruio_new(uint16 Act, uint8 Av, uint32 OpD, uint8 SaD)
Wrapper function for the constructor PruIo::PruIo().
adcStepmask
Wrapper enumerators for AdcStepMask.
@ AIN5
Activate Step 6 (default config: AIN5)
@ AIN2
Activate Step 3 (default config: AIN2)
@ AIN4
Activate Step 5 (default config: AIN4)
@ AIN7
Activate Step 8 (default config: AIN7)
@ AIN0
Activate Step 1 (default config: AIN0)
@ AIN6
Activate Step 7 (default config: AIN6)
@ AIN3
Activate Step 4 (default config: AIN3)
@ AIN1
Activate Step 2 (default config: AIN1)
struct timerArr timerArr
Wrapper structure for TimerArr.
struct timerUdt timerUdt
Wrapper structure for TimerUdt.
char * pruio_qep_config(pruIo *Io, uint8 Ball, uint32 PMax, float_t VHz, float_t Scale, uint8 Mo)
Wrapper function for QepMod::config().
pinMuxing
Wrapper enumerators for PinMuxing.
@ PRUIO_GPIO_OUT1
GPIO output high (no resistor).
@ PRUIO_GPIO_IN
GPIO input (no resistor).
@ PRUIO_NO_PULL
No resistor connected (&b001000).
@ PRUIO_PULL_UP
Pullup resistor connected (&b010000).
@ PRUIO_RX_ACTIV
Input receiver enabled (&b100000).
@ PRUIO_PULL_DOWN
Pulldown resistor connected (&b000000).
@ PRUIO_GPIO_IN_0
GPIO input (pulldown resistor).
@ PRUIO_GPIO_IN_1
GPIO input (pullup resistor).
@ PRUIO_GPIO_OUT0
GPIO output low (no resistor).
char * pruio_cap_config(pruIo *Io, uint8 Ball, float_t FLow)
Wrapper function for CapMod::config().
struct qepMod qepMod
Wrapper structure for QepMod.
char * pruio_pwm_Value(pruIo *Io, uint8 Ball, float_t *Hz, float_t *Du)
Wrapper function for PwmMod::Value().
struct pruIo pruIo
forward declaration
struct adcSet adcSet
Wrapper structure for AdcSet.
char * pruio_adc_setStep(pruIo *Io, uint8 Stp, uint8 ChN, uint8 Av, uint8 SaD, uint32 OpD)
Wrapper function for AdcUdt::setStep().
char * pruio_gpio_config(pruIo *Io, uint8 Ball, uint8 Modus)
Wrapper function for GpioUdt::config().
struct gpioArr gpioArr
Wrapper structure for GpioArr.
char * pruio_qep_Value(pruIo *Io, uint8 Ball, uint32 *Posi, float_t *Velo)
Wrapper function for QepMod::Value().
char * pruio_rb_start(pruIo *Io)
Wrapper function for PruIo::rb_start().
void pruio_destroy(pruIo *Io)
Wrapper function for the destructor PruIo::~PruIo().
struct pwmMod pwmMod
Wrapper structure for PwmMod.
unsigned char uint8
8 bit unsigned integer data type.
activateDevice
Wrapper enumerators for ActivateDevice.
@ PRUIO_DEF_ACTIVE
Activate all subsystems.
@ PRUIO_ACT_FREMUX
Activate free LKM muxing.
@ PRUIO_ACT_TIM5
Activate TIMER-5.
@ PRUIO_ACT_GPIO0
Activate GPIO-0.
@ PRUIO_ACT_GPIO2
Activate GPIO-2.
@ PRUIO_ACT_GPIO3
Activate GPIO-3.
@ PRUIO_ACT_PWM2
Activate PWMSS-2 (including eCAP, eQEP, ePWM).
@ PRUIO_ACT_PWM1
Activate PWMSS-1 (including eCAP, eQEP, ePWM).
@ PRUIO_ACT_TIM7
Activate TIMER-7.
@ PRUIO_ACT_ADC
Activate ADC.
@ PRUIO_ACT_PWM0
Activate PWMSS-0 (including eCAP, eQEP, ePWM).
@ PRUIO_ACT_TIM4
Activate TIMER-4.
@ PRUIO_ACT_TIM6
Activate TIMER-6.
@ PRUIO_ACT_GPIO1
Activate GPIO-1.
@ PRUIO_ACT_PRU1
Activate PRU-1 (= default, instead of PRU-0).
char * pruio_gpio_setValue(pruIo *Io, uint8 Ball, uint8 Modus)
Wrapper function for GpioUdt::setValue().
uint32 pruio_adc_mm_trg_pin(pruIo *Io, uint8 Ball, uint8 GpioV, uint16 Skip)
Wrapper function for AdcUdt::mm_trg_pin().
char * pruio_tim_setValue(pruIo *Io, uint8 Ball, float_t Dur1, float_t Dur2, uint16 Mode)
Wrapper function for TimerUdt::setValue().
This file synchronizes parameters between FreeBASIC, C and PASM source code.
#define PRUIO_AZ_GPIO
The number of GPIO subsystems (minus one)
#define PRUIO_AZ_PWMSS
The number of PWM subsystems (minus one)
#define PRUIO_AZ_BALL
The number of CPU balls to handle (minus one)
C header file for interrupt controller defines.
#define VHz
The frequency for speed measurement.
Init data structure for the interrupt controller setting.
Wrapper structure for AdcSet.
uint32 IDLECONFIG
Register at offset 58h (chap. 12.5.1.16).
uint32 ClAd
Clock address.
uint32 REVISION
Register at offset 00h (chap. 12.5.1.1).
uint32 FIFO1THRESHOLD
Register at offset F4h (chap. 12.5.1.55).
uint32 ADCSTAT
Register at offset 44h (chap. 12.5.1.11).
uint32 SYSCONFIG
Register at offset 10h (chap. 12.5.1.2).
uint32 IRQSTATUS_RAW
Register at offset 24h (chap. 12.5.1.3).
uint32 DMA1REQ
Register at offset F8h (chap. 12.5.1.56).
uint32 DMAENABLE_CLR
Register at offset 3Ch (chap. 12.5.1.9).
uint32 CTRL
Register at offset 40h (chap. 12.5.1.10).
uint32 ADC_CLKDIV
Register at offset 4Ch (chap. 12.5.1.13).
uint32 FIFO1COUNT
Register at offset F0h (chap. 12.5.1.54).
uint32 DMAENABLE_SET
Register at offset 38h (chap. 12.5.1.8).
uint32 ADC_MISC
Register at offset 50h (chap. 12.5.1.14).
uint32 STEPENABLE
Register at offset 54h (chap. 12.5.1.15).
struct adcSteps St_p[16+1]
step configuration (chap. 12.5.1.16 ff, charge step + 16 steps, by default steps 1 to 8 are used for ...
uint32 IRQSTATUS
Register at offset 28h (chap. 12.5.1.4).
uint32 DeAd
Subsystem address.
uint32 ADCRANGE
Register at offset 48h (chap. 12.5.1.12).
uint32 DMA0REQ
Register at offset ECh (chap. 12.5.1.53).
uint32 IRQENABLE_SET
Register at offset 2Ch (chap. 12.5.1.5).
uint32 IRQENABLE_CLR
Register at offset 30h (chap. 12.5.1.6).
uint32 IRQWAKEUP
Register at offset 34h (chap. 12.5.1.7).
uint32 FIFO0COUNT
Register at offset E4h (chap. 12.5.1.51).
uint32 FIFO0THRESHOLD
Register at offset E8h (chap. 12.5.1.52).
Wrapper structure for AdcSteps.
uint32 Confg
Context for configuration register.
uint32 Delay
Context for delay register.
Wrapper structure for AdcUdt.
uint32 Samples
Number of samples (specifies run mode: 0 = config, 1 = IO mode, >1 = MM mode).
uint16 ChAz
The number of active steps.
uint32 TimerVal
Timer value in [ns].
uint16 * Value
Fetched ADC samples.
adcSet * Conf
Current subsystem configuration, used in PruIo::config().
pruIo * Top
Pointer to the calling PruIo instance.
uint32 InitParA
Offset to read data block offset.
uint16 LslMode
Bit shift modus (0 to 4, for 12 to 16 bits).
adcSet * Init
Initial subsystem configuration, used in the destructor PruIo::~PruIo().
Wrapper structure for BallSet.
uint32 DeAd
Base address of Control Module subsystem.
uint8 Value[PRUIO_AZ_BALL+1]
The values of the pad control registers.
Wrapper structure for GpioArr.
uint32 DeAd
Base address of GPIO subsystem + 0x100.
uint32 Mix
Current state of pins (IN&OUT mixed).
uint32 DATAIN
Current Value of DATAIN register (IO).
uint32 DATAOUT
Current Value of DATAOUT register (IO).
Wrapper structure for GpioSet.
uint32 ClAd
Clock address.
uint32 SYSCONFIG
Register at offset 10h (chap. 25.4.1.2).
uint32 IRQSTATUS_CLR_0
Register at offset 3Ch (chap. 25.4.1.10).
uint32 DEBOUNCINGTIME
Register at offset 154h (chap. 25.4.1.24).
uint32 EOI
Register at offset 20h (chap. 25.4.1.3).
uint32 DEBOUNCENABLE
Register at offset 150h (chap. 25.4.1.23).
uint32 CLEARDATAOUT
Register at offset 190h (chap. 25.4.1.25).
uint32 DATAIN
Register at offset 138h (chap. 25.4.1.17).
uint32 CTRL
Register at offset 130h (chap. 25.4.1.15).
uint32 LEVELDETECT1
Register at offset 144h (chap. 25.4.1.20).
uint32 IRQSTATUS_SET_0
Register at offset 34h (chap. 25.4.1.8).
uint32 IRQWAKEN_0
Register at offset 44h (chap. 25.4.1.12).
uint32 IRQWAKEN_1
Register at offset 48h (chap. 25.4.1.13).
uint32 IRQSTATUS_SET_1
Register at offset 38h (chap. 25.4.1.9).
uint32 FALLINGDETECT
Register at offset 14Ch (chap. 25.4.1.22).
uint32 IRQSTATUS_CLR_1
Register at offset 40h (chap. 25.4.1.11).
uint32 LEVELDETECT0
Register at offset 140h (chap. 25.4.1.19).
uint32 SETDATAOUT
Register at offset 194h (chap. 25.4.1.26).
uint32 RISINGDETECT
Register at offset 148h (chap. 25.4.1.21).
uint32 IRQSTATUS_0
Register at offset 2Ch (chap. 25.4.1.6).
uint32 DeAd
Subsystem address.
uint32 IRQSTATUS_1
Register at offset 30h (chap. 25.4.1.7).
uint32 SYSSTATUS
Register at offset 114h (chap. 25.4.1.14).
uint32 DATAOUT
Register at offset 13Ch (chap. 25.4.1.18).
uint32 IRQSTATUS_RAW_1
Register at offset 28h (chap. 25.4.1.5).
uint32 OE
Register at offset 134h (chap. 25.4.1.16).
uint32 REVISION
Register at offset 00h (chap. 25.4.1.1).
uint32 IRQSTATUS_RAW_0
Register at offset 24h (chap. 25.4.1.4).
Wrapper structure for GpioUdt.
gpioSet * Conf[PRUIO_AZ_GPIO+1]
Current subsystem configuration, used in PruIo::config().
uint32 Mask
The bit mask to manipulate.
uint8 Mode
The mode for pinmuxing.
uint8 Fe2
Future expansion.
uint8 Indx
The GPIO subsystem index.
gpioArr * Raw[PRUIO_AZ_GPIO+1]
Pointer to current raw subsystem data (IO), all 32 bits.
uint8 Fe1
Future expansion.
pruIo * Top
pointer to the calling PruIo instance
uint32 InitParA
Offset to read data block offset.
gpioSet * Init[PRUIO_AZ_GPIO+1]
Initial subsystem configuration, used in the destructor PruIo::~PruIo().
Wrapper structure for PruIo.
void * MOffs
Configuration offset for modules.
int16 ParOffs
The offset for the parameters of a module.
capMod * Cap
Pointer to eCAP module structure (in PWMSS subsystem).
uint32 PruNo
The PRU number to use (defaults to 1).
uint32 EAddr
The address of the external memory (PRUSS-DDR).
uint32 ESize
The size of the external memory (PRUSS-DDR).
char * MuxAcc
pathfile for dtbo pinmuxing
uint8 * BallInit
Pointer for original Ball configuration.
struct __pruss_intc_initdata * IntcInit
Interrupt settings (we also set default interrupts, so that the other PRUSS can be used in parallel).
char * Errr
Pointer for error messages.
uint32 PruIRam
The PRU instruction ram to load.
pwmMod * Pwm
Pointer to ePWM module structure (in PWMSS subsystem).
uint8 BallGpio[PRUIO_AZ_BALL+1]
List of GPIO numbers, corresponding to ball index.
uint8 * BallConf
Pointer to ball configuration (CPU pin muxing).
pwmssUdt * PwmSS
Pointer to PWMSS subsystem structure.
qepMod * Qep
pointer to eQEP module structure (in PWMSS subsystem)
uint32 * DRam
Pointer to access PRU DRam.
timerUdt * Tim
Pointer to the TimSS structure (for homogenous API).
int16 DevAct
Active subsystems.
uint32 PruDRam
The PRU data ram.
uint32 PruIntNo
The PRU interrupt number.
timerUdt * TimSS
Pointer to TIMER subsystem structure.
gpioUdt * Gpio
Pointer to GPIO subsystem structure.
ballSet * Conf
The subsystems register data used by libpruio (current local data).
uint32 BbType
Type of Beaglebone board (1 = Pocket-, 0 = others)
adcUdt * Adc
Pointer to ADC subsystem structure.
uint32 MuxFnr
FreeBASIC file number for LKM pinmuxing.
void * ERam
Pointer to read PRU external ram.
void * DConf
Pointer to block of subsystems configuration data.
ballSet * Init
The subsystems register data at start-up (to restore subsystems at the end).
void * DInit
Pointer to block of subsystems initial data.
uint32 DSize
The size of a data block (DInit or DConf).
Wrapper structure for PwmMod.
uint16 AqCtl[1+1][PRUIO_AZ_PWMSS+1][2+1]
Initializers for Action Qualifier for ePWM modules (see PWM).
uint16 ForceUpDown
< Switch to force up-down counter for ePWM modules.
char * E0
< Common error message.
char * E3
< Common error message.
pruIo * Top
pointer to the calling PruIo instance
char * E4
Common error message.
uint16 Cntrl[PRUIO_AZ_PWMSS+1]
< Initializers TBCTL register for ePWM modules (see PWM).
char * E2
< Common error message.
char * E1
< Common error message.
Wrapper structure for PwmssArr.
uint32 NPos
< New position latch (QEP).
uint32 C2
< Period time counter value (CAP).
uint32 PLat
New period timer latch (QEP).
uint32 C1
< On time counter value (CAP).
uint32 CMax
< Maximum counter value (CAP).
uint32 DeAd
Subsystem address.
uint32 QPos
< Current position counter (QEP).
uint32 OPos
< Old position latch (QEP).
Wrapper structure for PwmssSet.
uint16 QEPCTL
Control Register (chap. 15.4.3.14).
uint16 ETPS
Event-Trigger Pre-Scale Register.
uint16 DBRED
Dead-Band Generator Rising Edge Delay Count Register.
uint16 CMPAHR
Extension for HRPWM Counter-Compare A Register.
uint16 AQCTLA
Action-Qualifier Control Register for Output A (EPWMxA).
uint16 DBFED
Dead-Band Generator Falling Edge Delay Count Register.
uint16 ETSEL
Event-Trigger Selection Register.
uint16 QCPRDLAT
Capture Period Latch Register (chap. 15.4.3.24).
uint32 DeAd
Subsystem address.
uint16 QDECCTL
Decoder Control Register (chap. 15.4.3.12).
uint16 TZSEL
Trip-Zone Select Register.
uint16 QCAPCTL
Capture Control Register (chap. 15.4.3.15).
uint16 QWDTMR
Watchdog Timer Register (chap. 15.4.3.10).
uint16 AQSFRC
Action-Qualifier Software Force Register.
uint16 AQCTLB
Action-Qualifier Control Register for Output B (EPWMxB).
uint32 QPOSILAT
Index Position Latch Register (chap. 15.4.3.5).
uint32 CAP2
Capture 2 Register (chap. 15.3.4.1.4).
uint32 CAP3
Capture 3 Register (chap. 15.3.4.1.5).
uint32 SYSCONFIG
System Configuration Register (chap. 15.1.3.2).
uint16 ETFLG
Event-Trigger Flag Register.
uint16 TZFRC
Trip-Zone Force Register.
uint16 empty
Adjust at uint32 border.
uint32 IDVER
IP Revision Register (chap. 15.1.3.1).
uint32 QPOSMAX
Maximum Position Count Register (chap. 15.4.3.3).
uint32 QUPRD
Unit Period Register (chap. 15.4.3.9).
uint32 QPOSLAT
Position Counter Latch Register (chap. 15.4.3.7).
uint32 QPOSCNT
Position Counter Register (chap. 15.4.3.1).
uint32 CTRPHS
Counter Phase Offset Value Register (chap. 15.3.4.1.2).
uint16 ECCTL2
Capture Control Register 2 (chap. 15.3.4.1.8).
uint32 ClAd
Clock address.
uint16 QWDPRD
Watchdog Period Register (chap. 15.4.3.11).
uint16 CMPA
Counter-Compare A Register.
uint16 QFRC
Interrupt Force Register (chap. 15.4.3.19).
uint16 QCTMRLAT
Capture Timer Latch Register (chap. 15.4.3.23).
uint16 QPOSCTL
Position-Compare Control Register (chap. 15.4.3.15).
uint16 CMPCTL
Counter-Compare Control Register.
uint16 CMPB
Counter-Compare B Register.
uint16 TBPHSHR
Extension for HRPWM Phase Register.
uint32 TSCTR
Time-Stamp Counter Register (chap. 15.3.4.1.1).
uint16 TZEINT
Trip-Zone Enable Interrupt Register.
uint32 QUTMR
Unit Timer Register (chap. 15.4.3.8).
uint16 PCCTL
PWM-Chopper Control Register.
uint16 ECFRC
Capture Interrupt Force Register (chap. 15.3.4.1.12).
uint16 TBCTL
Time-Base Control Register.
uint16 ECFLG
Capture Interrupt Flag Register (chap. 15.3.4.1.10).
uint16 QCTMR
Capture Timer Register (chap. 15.4.3.21).
uint16 DBCTL
Dead-Band Generator Control Register.
uint16 QEPSTS
Status Register (chap. 15.4.3.20).
uint16 HRCTL
HRPWM Control Register.
uint32 CAP1
Capture 1 Register (chap. 15.3.4.1.3).
uint16 QCLR
Interrupt Clear Register (chap. 15.4.3.18).
uint16 ETFRC
Event-Trigger Force Register.
uint16 ECCLR
Capture Interrupt Clear Register (chap. 15.3.4.1.11).
uint32 CAP_REV
Revision ID Register (chap. 15.3.4.1.13).
uint32 QPOSCMP
Position-Compare Register 2/1 (chap. 15.4.3.4).
uint16 TBSTS
Time-Base Status Register.
uint16 TZCLR
Trip-Zone Clear Register.
uint32 QPOSSLAT
Strobe Position Latch Register (chap. 15.4.3.6).
uint16 TBCNT
Time-Base Counter Register.
uint16 ECEINT
Capture Interrupt Enable Register (chap. 15.3.4.1.9).
uint32 QPOSINIT
Position Counter Initialization Register (chap. 15.4.3.2).
uint16 ETCLR
Event-Trigger Clear Register.
uint16 AQCSFRC
Action-Qualifier Continuous S/W Force Register Set.
uint16 QFLG
Interrupt Flag Register (chap. 15.4.3.17).
uint32 CAP4
Capture 4 Register (chap. 15.3.4.1.6).
uint16 TBPRD
Time-Base Period Register.
uint32 CLKSTATUS
Clock Status Register (chap. 15.1.3.4).
uint16 ECCTL1
Capture Control Register 1 (chap. 15.3.4.1.7).
uint16 QCPRD
Capture Period Register (chap. 15.4.3.22).
uint16 TBPHS
Time-Base Phase Register.
uint16 QEINT
Interrupt Enable Register (chap. 15.4.3.16).
uint32 QEP_REV
Revision ID (chap. 15.4.3.25).
uint16 TZCTL
Trip-Zone Control Register.
uint16 TZFLG
Trip-Zone Flag Register.
uint32 CLKCONFIG
Clock Configuration Register (chap. 15.1.3.3).
Wrapper structure for PwmssUdt.
pwmssSet * Conf[PRUIO_AZ_PWMSS+1]
Current subsystem configuration, used in PruIo::config().
pruIo * Top
pointer to the calling PruIo instance
const uint16 CapMod
Value for ECCTL2 in CAP mode (&b0011010110).
uint32 InitParA
Offset to read data block offset.
pwmssArr * Raw[PRUIO_AZ_PWMSS+1]
Pointer to current raw subsystem data (IO).
pwmssSet * Init[PRUIO_AZ_PWMSS+1]
Initial subsystem configuration, used in the destructor PruIo::~PruIo().
Wrapper structure for QepMod.
float_t FVh[PRUIO_AZ_PWMSS+1]
< Factor for high velocity measurement.
pruIo * Top
pointer to the calling PruIo instance
uint32 Prd[PRUIO_AZ_PWMSS+1]
Period value to switch velocity measurement.
char * E0
< Common error message.
char * E1
< Common error message.
char * E2
Common error message.
float_t FVl[PRUIO_AZ_PWMSS+1]
Factor for low velocity measurement.
Wrapper structure for TimerArr.
uint32 DeAd
Subsystem address.
uint32 CMax
< Maximum counter value.
uint32 TCAR2
Current value of TCRR register (IO, RB).
uint32 TCAR1
< Current value of TCAR2 register (IO, RB).
Wrapper structure for TimerSet.
uint32 IRQWAKEEN
< Timer IRQ Wakeup Enable Register (offset 34h, see ARM Reference Guide, chapter 20....
uint32 TCAR1
< Timer Capture Register (offset 50h, see ARM Reference Guide, chapter 20.1.5.15 ).
uint32 TTGR
< Timer Trigger Register (offset 44h, see ARM Reference Guide, chapter 20.1.5.12 ).
uint32 IRQENABLECLR
< Timer Interrupt Enable Clear Register (offset 30h, see ARM Reference Guide, chapter 20....
uint32 TMAR
< Timer Match Register (offset 4Ch, see ARM Reference Guide, chapter 20.1.5.14 ).
uint32 TWPS
< Timer Write Posting Bits Register (offset 48h, see ARM Reference Guide, chapter 20....
uint32 TCRR
< Timer Counter Register (offset 3Ch, see ARM Reference Guide, chapter 20.1.5.10 ).
uint32 IRQSTATUSRAW
< Timer Status Raw Register (offset 24h, see ARM Reference Guide, chapter 20.1.5.4 ).
uint32 TCLR
< Timer Control Register (offset 38h, see ARM Reference Guide, chapter 20.1.5.9 ).
uint32 TIOCPCFG
< Timer OCP Configuration Register (offset 10h, see ARM Reference Guide, chapter 20....
uint32 DeAd
Subsystem address.
uint32 TSICR
< Timer Synchronous Interface Control Register (offset 54h, see ARM Reference Guide,...
uint32 TLDR
< Timer Load Register (offset 40h, see ARM Reference Guide, chapter 20.1.5.11 ).
uint32 IRQENABLESET
< Timer Interrupt Enable Set Register (offset 2Ch, see ARM Reference Guide, chapter 20....
uint32 IRQEOI
< Timer IRQ End-of-Interrupt Register (offset 20h, see ARM Reference Guide, chapter 20....
uint32 TCAR2
Timer Capture Register (offset 58h, see ARM Reference Guide, chapter 20.1.5.17 ).
uint32 ClAd
Clock address.
uint32 IRQSTATUS
< Timer Status Register (offset 28h, see ARM Reference Guide, chapter 20.1.5.5 ).
uint32 TIDR
< Register at offset 00h (see ARM Reference Guide, chapter 20.1.5.1 ).
Wrapper structure for TimerUdt.
timerSet * Conf[PRUIO_AZ_GPIO+1]
Current subsystem configuration, used in PruIo::config().
uint32 Tim_Low
< Control register for Timer low.
char * E0
< Common error message.
uint32 InitParA
< Offset to read data block offset.
uint32 TimHigh
< Control register for Timer high.
char E2
Common error message.
timerSet * Init[PRUIO_AZ_GPIO+1]
Initial subsystem configuration, used in the destructor PruIo::~PruIo().
uint32 CapMode
Control register for CAP input mode.
timerArr * Raw[PRUIO_AZ_GPIO+1]
Pointer to current raw subsystem data (IO), all 32 bits.
uint32 PwmMode
< Control register for PWM output mode.
char E1
< Common error message.
uint32 TimMode
< Control register for Timer mode.
pruIo * Top
Pointer to the calling PruIo instance.